Integrated circuits (IC's) and other semiconductor devices are extremely sensitive to the high voltages that may be generated by contact with an ESD event. As such, electrostatic discharge (ESD) protection circuitry is essential for integrated circuits. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC's and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
In order to protect against these over-voltage conditions, protection devices such as silicon controlled rectifiers (SCR) or Metal Oxide Semiconductor (MOS) devices have been incorporated within the circuitry to provide a discharge path for the high current produced by the discharge of the high electrostatic potential. Prior to an ESD event, the protection device is in a non-conductive state. Once the ESD event is detected, the protection device then changes to a conductive state to shunt the current to ground. The protection device maintains this conductive state until the voltage is discharged to a safe level.
When protecting an IC (Integrated Circuit) against ESD (Electro Static Discharge) stress, the classic approach is to use a number of independently triggered placed power clamps (PC1 to PCn). FIG. 1A shows an illustration of the classical approach in which four independently triggered power clamps PC1 120, PC2 122, PC3 124, and PC4 126 are used. PC1 120 and PC3 124 are placed in a Vdd 128 power pad cell, and PC2 122 and PC4 126 are placed in a Vss 130 ground pad cell. In between the power and ground pad cells the power and ground busses have a certain amount of bus resistance RVdd 132 and RVss 134. When using this approach, the voltage over an I/O or core element is not only dependent on the characteristics of the clamps itself but also on the bus resistance between this element and the clamp. Usually the ESD designer assumes a worst case scenario in which only one clamp triggers, and in which this clamps will take all the current. Because one cannot be sure which and how many clamps will trigger, this is a necessary approach. However, this approach leads to less area efficient, and sometimes over dimensioned or unrealistically big ESD protection device sizes. Especially in technologies which have a decreased ESD design windows, increased dynamic on resistance of protection devices and decreased heat dissipation characteristics of the active silicon film, the need to ensure more clamps to trigger is high.
When using the classical approach of uncoupled clamps, triggering of multiple clamps highly depends on the Vt2/Vt1 relationship, with Vt2 the failure voltage and Vt1 the trigger voltage of the clamp, and the resistance of the busses in between the individual clamps. Imagine e.g. in FIG. 1A that we stress the Vdd1 128 pin positively to Vss2 130. In such a case all four clamps have theoretically the same chance of triggering.
Let's assume that PC1 120 triggers first. Then the voltages over the other clamps are given by:VPC2=VPC1+RVss*I VPC3=VPC1+2*RVss*I VPC4=VPC1+3*RVss*I 
Note that I is the current and V is the voltage with * being a multiplication sign. Also, VPC1, VPC2, VPC3 AND VPC4 are voltages at clamps 1, 2, 3 and 4 respectively. Clamps PC2 122 PC3 124 and PC4 126 will also trigger when the following voltage relationship becomes true:VPC2>Vt1 VPC3>Vt1 VPC1>Vt1 
The clamp, PC4 126 which is closest to the ground pad has the biggest chance to trigger next. However, whether PC4 126 and other clamps will trigger depends greatly on two factors. First, Vt2 being greater than Vt1 or not, and the second on the amount of bus resistance between the different clamps.
Now let's assume another case (again positive stress from Vdd1 to Vss2) in which power clamp PC2 122 first triggers. Then the voltages over the other claims are given by:VPC1=VPC2+RVdd*I VPC3=VPC2+RVss*I VPC4=VPC2+2*RVss*I 
Clamps PC1 120, PC3 124 and PC4 126 will also trigger when the following voltage relationship becomes true:VPC1>Vt1 VPC3>Vt1 VPC4>Vt1 
The clamp PC4 128, which is closest to the ground pad has the biggest chance to trigger next. However, whether PC4 126 and other clamps will trigger depends greatly on two factors. First, Vt2 being great than Vt1 or not, and second on the size of the bus resistance between the different clamps.
Especially when Vt2>Vt1, we can more safely assume that more than one clamp will take the current and in such a case the individual clamps can be downsized. However, many technologies produce ESD protection devices which have a deep snapback, and which have Vt2<Vt1. In such cases, we cannot assume that multiple clamps will take the ESD discharge current. Moreover, in technologies which are characterized by a low heat dissipating efficiency (low It2), high Ron, and decreased ESD design windows (decreased Gate Oxide (GOX) breakdown voltages), the demand to couple the ESD is high. In such a case one needs to ensure or initiate the simultaneous triggering of multiple clamps to ensure multi-clamp triggering.
This problem isn't limited to different clamps but it's also possible in one clamp that consists of many separate fingers. FIG. 1B depicts a schematic diagram of a prior art multi-fingered SCR ESD protection circuit 100, which serves as protection circuitry for an integrated circuit (not shown). The circuit 100 having multiple SCR fingers, and is illustratively depicted in FIG. 1B having three SCR “fingers” 102, 104 and 106. Each finger works as a separate clamp, but is layouted as one whole clamp. The SCR protection circuit 100 comprises a first trigger device 108, a first SCR 102 (i.e. “first finger”), a second SCR 104 (i.e. “second finger”) and a third SCR 106 (i.e. “third finger”). The first SCR 102 further comprises PNP transistor and an NPN transistor. In particular, the first SCR 102 includes an anode 108, which is connected to a pad (not shown) and to one side of a resistor 114. The resistor 114 represents the resistance of the N−well (or an external resistor), which is seen at the base of the PNP transistor of the SCR 102. Also, included is a cathode 112 which is connected to a ground (not shown) and to one side of a resistor 110. The resistor 110 represents the resistance of the P−well (or an external resistor) which is seen at the base of NPN transistor. The second and third SCRs 104 and 106 are formed exactly in the same manner as described with regard to the first SCR 102. When SCRs 102, 104, 106 are placed in parallel as shown in FIG. 1B multifinger triggering is a potential issue. The typical solution is to connect a first triggering device G1 116 and/or a second triggering device G2 118, as shown in FIG. 1B such that the voltage drop seen by all anode/G2 respectively G1/Cathode diodes is the same. However, when the SCR goes into high injection mode, the structure acts like a PIN diode, such that the G1 and G2 taps do not control the voltage at the Nwell/Pwell junction anymore. This renders the multifinger triggering solution of connection the gates of the different SCRs ineffective. Therefore, there is a need in the art for a multi-fingered SCR protection device having an enhanced and reliable triggering mechanism.
A SCR in its basic form is depicted as a prior art in FIG. 1C with an anode 136 and cathode 138. It is regarded as a PNPN structure, formed by P+, N− well, P−substrate and N+. When using SCR's to protect a chip against ESD, one SCR is needed for each possible current path. As seen in FIG. 1C, each SCR takes some area to implement. The large number of clamps (each current path needs its own clamp) increases the needed area for the ESD protection. So, there is a need in the art to incorporate different clamps into one clamp and also to couple these clamps to overcome the disadvantages of the prior art.